1. Field of Invention
The present invention relates to a method of fabricating isolation for an integrated circuit (IC) device. More particularly, the present invention relates to a method of fabricating shallow trench isolation (STI).
2. Description of Related Art
A complete circuit such as an integrated circuit (IC) is usually composed of thousands of MOS transistors. To prevent a short circuit between these adjacent transistors, an isolation structure for electrical isolation between adjacent transistors must be added.
Field oxide (FOX), manufactured by local oxidation silicon (LOCOS), is used conventionally as an isolation structure in the semiconductor process. However, there are still many issues within the LOCOS technique, including conventional problems related to the stress mechanism, the formation of a bird's beak around a LOCOS field isolation structure, etc. The problem resulting from the bird's beak, in particular, has made the LOCOS field isolation structure ineffective for isolation in small devices.
To accommodate the tendency towards shrinkage of the critical dimension (CD) of devices, shallow trench isolation, effective for isolation in small devices, has become the preferred isolation technique for the deep sub-micron process.
FIGS. 1A through 1C are schematic, cross-sectional views showing the progression of manufacturing steps in fabricating a conventional shallow trench isolation.
First, as shown in FIG. 1A, a substrate 100 is provided. A pad oxide layer 102 and a mask layer 104 are sequentially formed thereon. Next, a photolithographic and etching operation is conducted to form a shallow trench 106 that extends into the substrate 100. The pad oxide layer 102 can be formed using a thermal oxidation method and the mask layer 104 can be formed using a chemical vapor deposition (CVD) method.
A liner oxide layer 108 is then formed on the exposed surface of the substrate 100 in the shallow trench 106. The liner oxide layer 108 can be formed using a thermal oxidation method
Referring to FIG. 1B, an oxide layer 110 is formed on the substrate 100 to fill the shallow trench 106. The oxide layer 110 can be formed by first forming an oxide layer (not shown in the figure) over the mask layer 104 and filling the shallow trench 106. Next, a chemical mechanical polishing (CMP) process is introduced to remove the oxide layer above the mask layer 104.
The oxide layer 110 is formed by, for example, chemical vapor deposition with a gas source of ozone (O.sub.3) and tetra-ethyl-ortho-silicate (TEOS), or by high density plasma chemical vapor deposition (HDPCVD).
Referring to FIG. 1C, the pad oxide layer 102 and the mask layer 104 are removed by wet etching, and a STI is completed.
However, since different methods are used to form the pad oxide layer 102 and the oxide layer 110, respectively, the pad oxide layer 102 and the oxide layer 110 have different densities.
In general, the pad oxide layer 102 formed by thermal oxidation has a better etching resistance than the oxide layer 110 formed by chemical vapor deposition. That is, the etching rate for the pad oxide layer 102 is lower than that for the oxide layer 110 in the same etching process. Thus, in the prior art, when the pad oxide layer 102 and the oxide layer 110 are removed in an etching process, the oxide layer 110 in the STI 106 is more easily etched than the pad oxide layer 102 does. Thus, a cavity 112 is formed on the surface of the oxide layer 110 in the vicinity of the interface between the STI 106 and the substrate 100.
Due to the cavity 112 in the oxide layer 110 that fills the STI 106, a kink effect is induced during the operation of the device. Thus, the isolation of the STI may malfunction because of a significant subthreshold current, and the yield could be reduced.